1. Field of the Invention
The present invention relates to a semiconductor device having a protection circuit for securing protection against any voltage higher than a preset dielectric breakdown voltage, and to a semiconductor device having a protection circuit for protecting a to-be-protected semiconductor device from a damage, such as a dielectric breakdown resulting from an electrostatic discharge (hereinafter referred to as an ESD).
2. Description of the Related Art
In order to protect a semiconductor device from a damage resulting from the ESD, various protection circuits using a device such as an SCR and protection MOS transistor have conventionally been used. Generally, this type of protection circuit is formed between an external connection terminal liable to suffer the ESD from an outside and a reference terminal, for example, between a power supply terminal and a ground terminal, so as to prevent any damage resulting from the ESD to an internal circuit of the semiconductor device to be protected. When any high voltage caused by the ESD is applied to the external connection terminal, then the protection circuit detects this high voltage and allows the static electricity to be discharged onto the ground terminal. At this time, no zero voltage occurs in a discharge path of the protection circuit and a hold voltage resulting from the protection circuit is generated across the external connection terminal and the reference terminal. The hold voltage is also called a clamp voltage resulting from the protection circuit.
when the shrinkage of any element, such as an MOS transistor, in the semiconductor device to be protected is progressed, the dielectric breakdown voltage of its gate insulating film is lowered and there is a possibility that, if the hold voltage of the protection circuit becomes higher than such dielectric breakdown voltage, there will occur a dielectric breakdown of the gate insulating film. Therefore, there is also a necessity for the hold voltage to be set to a lowest possible extent.
For example, in FIG. 11 of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, No. 2 FEBRUARY 2003, “Substrate-Triggered ESD Protection Circuit Without Extra Process Modification” Ming-Dou Ker, Senior Member, IEEE, and Tung-Yang chen, Member, IEEE, a protection circuit is shown as a combination of, between an input or output pad of a to-be-protected semiconductor device and a VSS terminal, an ESD detection circuit comprising a capacitor (C) and a resistor (R) and an NMOS transistor which is used as a clamp element. However, it is necessary to provide voltages VCE, VBE of an NPN bipolar transistor acting as a parasitic transistor for the NMOS transistor as well as a gate bias voltage exceeding a voltage Vth of another NMOS transistor acting as a base current supply element of this parasitic NPN bipolar transistor. The parasitic NPN bipolar transistor and NMOS transistor, being connected as a series array, provide a clamp voltage of VBE+Vth. As a result, it is not possible to provide an adequately low hold voltage, that is, clamp voltage lower than the value VBE+Vth.